1. Field of the Invention
The present invention relates to the formation of planarized insulating layers on semiconductor substrates having irregular surface features and more particularly, to the use of a non-etchback spin-on-glass techniques for planarizing over micrometer and submicrometer surface features.
2. Description of the Prior Art
Today's Ultra Large Scale Integration (ULSI) on the semiconductor substrate are in part due to advances in photolithographic techniques and to advances in etching. For example, improvements in optical resolution and photoresist materials have lead to submicrometer resolution in photoresist image sizes. Likewise, the replacement of wet etching with directional plasma etching has resulted in submicrometer patterns being etched in the substrate and in the conducting and insulating layers that are deposited on the substrate surface and make up the integrated circuits.
However, the accumulated effect of depositing these layers and the etching of patterns in the layers, one on top of the other as resulted in irregular or substantially non-planar surface features on the otherwise microscopically planar substrate. This rough topography is substantially worse at the later processing step where multilayer metallurgy is used to wire up the discrete devices on the integrated circuit chip.
These advancements in down scaling of devices and inter-connecting metal wiring have not come without certain technological problems. For example, the improvement in photolithographic resolution require a more shallow depth of focus during optical exposure of the photoresist. This results in unwanted distorted photoresist images over non-planar portions of the substrates. Likewise, anisotropic etching to pattern the various conducting layers over the non-planar surface can result in residue on the sidewalls of the underlying patterns which can lead to intra-level shorts. In addition, thinning of narrow inter-connecting metal lines over steps in underlying patterned layers can result in low yield and early failure of the circuit. This is especially true at high current densities where electromigration of the metal atoms in the line can lead to voids and open lines or can result in extrusion of metal between the closely spaced lines leading to shorts.
One approach of minimizing these topographic problems is to provide processes that preserve the planar nature of the substrate surface for receiving the next level of patterned layers. This planarization requirement is particularly important at the multilayer metallurgy levels, where the roughness of the surface topography can be quite severe.
Varies methods have been used for planarizing the dielectric layers that physically and electrically isolate these conducting metal layers. For example, some methods for forming planarized insulating layers over this rough topography include depositing bias sputtered silicon oxide, depositing and flowing of doped CVD oxides, such as phosphosilicate glass (PSG) and borophosphosilicate glass (BPSG), biased plasma enhanced CVD (PECVD) and similar techniques. However, many of these techniques are time consuming and require costly process equipment.
More recently, new techniques using spin-on-glasses are finding increasing use for forming interlevel insulator that can be planarized. This type of glass is of particular interest because the deposition process and planarization is relatively simple and the process utilizes low cost equipment. For example, the insulating layer is deposited by spin coating of a liquid precursor, similar to the spin application of photoresist. The layer is then dried to remove the solvents and baked on a hot plate or in a oven to cure the layer and to form an inorganic oxide by pyrolysis. For example, D. L. Yen U.S. Pat. No. 5,003,062 describes a method for forming a multilayer metallurgy using a spin-on-glass layer as part of the planarized insulating layer.
The formation of these planar insulating layers generally require the need of several spin-on-glass applications and bakes in order to achieve the necessary planarity. The spin-on-glass also suffers from other limitation when the coating material is dispensed on the wafer. For example, in the static dispense method, when the liquid is dispensed at zero wafer rotation and then the wafer is accelerated to high rotational speed the spin-on-glass layer can develop wave and crown like structures, while in the dynamic dispense method when the liquid is dispensed at low rotation speed and then the wafer is accelerated to high rotational speeds, striations can occur causing grooves or channels to appear near wafer edge. Also topographic features on the wafer can cause radial streaks to occur on the wafer. One approach for eliminating this problem was described by A. K. Weiss et al U.S. Pat. No. 4,971,931, in which a diffuser feature is provided on the wafer to disperse the liquid precursor.
When the patterned structure on the wafer surface in irregular in width or height, the recesses or cavities have aspect ratios which vary significantly. This is usually the case for the patterned conducting layers and as a result the coating of the wafer with spin-on-glass is further complicated. The aspect ratio being defined as the ratio of the height to the width of a recess or gap. For example, with the current trend in ULSI to even smaller image sizes, the aspect ratio for recesses between metal lines can approach 3:1. At conventional high spin speeds for coating the spin-on-glass, recesses having various aspect ratios do not consistently fill the same, making the planarization process more difficult. Therefore, there is strong need for planarizing process techniques which are less sensitive to the pattern geometry and therefore, the aspect ratio.